Figure 1. The general layout of a counter based pulse generator. The 100kHz clock frequency (C1) is divided by ten to give an alternative timebase of 10 kHz (C2). Either C1 or C2 can be used as clock for the delay generator, which determines the pulse separation, as well as for the pulse width generator.
The signals in the clocking block cb_counter are synchronised on the posedge of Clock, and by default all signals have a 4ns output (drive) skew and a #1step input (sample) skew. The skew determines how many time units away from the clock event a signal is to be sampled or driven.